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? semiconductor components industries, llc, 2001 may, 2001 rev. 5 1 publication order number: mc74ac74/d mc74ac74, mc74act74 dual d-type positive edge-triggered flip-flop the mc74ac74/74act74 is a dual dtype flipflop with asynchronous clear and set inputs and complementary (q,q ) outputs. information at the input is transferred to the outputs on the positive edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. after the clock pulse input threshold voltage has been passed, the data input is locked out and information present will not be transferred to the outputs until the next rising edge of the clock pulse input. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high ? outputs source/sink 24 ma ? act74 has ttl compatible inputs cp 1 c d 2 cp 2 13 14 12 11 10 9 8 2 1 34567 v cc c d1 d 1 cp 1 s d1 q 1 q 1 c d2 d 2 cp 2 s d2 q 2 q 2 c d 1 s d 1 q 1 d 1 s d 2 q 2 q 2 d 2 gnd q 1 figure 1. pinout: 14lead packages conductors (top view) pin assignment pin function d 1 , d 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 1 , q 2 , q 2 outputs tssop14 dt suffix case 948g 1 14 eiaj14 m suffix case 965 1 14 so14 d suffix case 751a http://onsemi.com 1 14 1 14 pdip14 n suffix case 646 device package shipping ordering information mc74ac74dt tssop14 96 units/rail mc74ac74dtr2 tssop14 2500 tape & reel mc74act74dt tssop14 96 units/rail mc74act74dtr2 tssop14 2500 tape & reel mc74ac74n pdip14 25 units/rail mc74ac74d soic14 55 units/rail mc74act74n pdip14 25 units/rail mc74ac74dr2 soic14 2500 tape & reel mc74act74d soic14 55 units/rail mc74act74dr2 soic14 2500 tape & reel mc74ac74m eiaj14 50 units/rail mc74ac74mel eiaj14 2000 tape & reel mc74act74m eiaj14 50 units/rail mc74act74mel eiaj14 2000 tape & reel see general marking information in the device marking section on page 7 of this data sheet. device marking information
mc74ac74, mc74act74 http://onsemi.com 2 truth table (each half) inputs outputs s d c d cp d q q l h x x h l h l x x l h l l x x h h h h h h l h h l l h h h l x q 0 q 0 note: h = high v oltage level l = low voltage level x = immaterial; = low-to-high clock transition q 0 (q 0 ) = previous q(q ) before low-to-high transition of clock figure 2. logic symbol s d1 q 1 cp 1 q 1 c d1 s d2 q 2 d 2 cp 2 q 2 cd 2 d 1 s d d cp c d q q figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage t emperature 65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac74, mc74act74 http://onsemi.com 3 recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v 150 t r , t f input rise and fall time (note ) ac devices exce p t schmitt in p uts v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f input rise and fall time (note ) v cc @ 4.5 v 10 ns/v t r , t f in ut rise and fall time (note ) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range 40 25 85 c i oh output current high 24 ma i ol output current low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input v oltage 4.5 2.25 3.15 3.15 v or v cc 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input v oltage 4.5 2.25 1.35 1.35 v or v cc 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = 50 m a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 m a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 m a v i =v cc gnd leakage current 5.5 0 . 1 1 . 0 m a v i = v cc , gnd i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 40 40 m a v in =v cc or gnd q supply current 5.5 4 . 0 40 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac74, mc74act74 http://onsemi.com 4 ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f max maximum clock 3.3 100 125 95 mhz 3 3 f max frequency 5.0 140 160 125 mh z 3 3 t plh propagation delay 3.3 5.0 8.0 12.5 4.0 13.0 ns 3 6 t plh gy c dn or s dn to q n or q n 5.0 3.5 6.0 9.0 3.0 10.0 ns 3 6 t phl propagation delay 3.3 4.0 10.5 12.0 3.5 13.5 ns 3 6 t phl gy c dn or s dn to q n or q n 5.0 3.0 8.0 9.5 2.5 10.5 ns 3 6 t plh propagation delay 3.3 4.5 8.0 13.5 4.0 16.0 ns 3 6 t plh gy c pn to q n or q n 5.0 3.5 6.0 10.0 3.0 10.5 ns 3 6 t phl propagation delay 3.3 3.5 8.0 14.0 3.5 14.5 ns 3 6 t phl gy c pn to q n or q n 5.0 2.5 6.0 10.0 2.5 10.5 ns 3 6 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set-up time, high or low 3.3 1.5 4.0 4.5 ns 39 t s d n to cp n 5.0 1.0 3.0 3.0 ns 3 9 t h hold time, high or low 3.3 2.0 0.5 0.5 ns 39 t h d n to cp n 5.0 1.5 0.5 0.5 ns 3 9 t w c pn or c dn or s dn 3.3 3.0 5.5 7.0 ns 36 t w pulse width 5.0 2.5 4.5 5.0 ns 3 6 t rec recovery time 3.3 2.5 0 0 ns 39 t rec c dn or s dn to cp 5.0 2.0 0 0 ns 3 9 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 http://onsemi.com 5 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input v oltage 5.5 1.5 2.0 2.0 v or v cc 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input v oltage 5.5 1.5 0.8 0.8 v or v cc 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = 50 m a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 m a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma i in maximum input 55 01 10 m a v i =v cc gnd leakage current 5.5 0 . 1 1 . 0 m a v i = v cc , gnd d i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc 2.1 v i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 40 40 m a v in =v cc or gnd q supply current 5.5 4 . 0 40 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f max maximum clock 50 145 210 125 mhz 33 f max maximum clock frequency 5. 0 14 5 210 12 5 mh z 3 3 t plh propagation delay 50 30 55 95 25 10 5 ns 36 t plh pro agation delay c dn or s dn to q n or q n 5. 0 3 . 0 5.5 9 .5 2 .5 10 .5 ns 3 6 t phl propagation delay 50 30 60 10 0 30 11 5 ns 36 t phl pro agation delay c dn or s dn to q n or q n 5. 0 3 . 0 6 . 0 10 . 0 3 . 0 11 .5 ns 3 6 t plh propagation delay 50 40 75 11 0 40 13 0 ns 36 t plh pro agation delay c pn to q n or q n 5. 0 4 . 0 7.5 11 . 0 4 . 0 13 . 0 ns 3 6 t phl propagation delay 50 35 60 10 0 30 11 5 ns 36 t phl pro agation delay c pn to q n or q n 5. 0 3 .5 6 . 0 10 . 0 3 . 0 11 .5 ns 3 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 http://onsemi.com 6 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s set-up time, high or low 50 10 30 35 ns 3 9 t s d n to cp n 5. 0 1 . 0 3 . 0 3 .5 ns 3 9 t h hold time, high or low 50 05 10 10 ns 3 9 t h d n to cp n 5. 0 0 .5 1 . 0 1 . 0 ns 3 9 t w c pn or c dn or s dn 50 30 50 60 ns 3 6 t w pulse width 5. 0 3 . 0 5. 0 6 . 0 ns 3 6 t rec recovery time 50 25 0 0 ns 3 9 t rec c dn or s dn to cp 5. 0 2 .5 0 0 ns 3 9 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 35 pf v cc = 5.0 v
mc74ac74, mc74act74 http://onsemi.com 7 marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip14 so14 tssop14 mc74ac74n awlyyww ac74 awlyww ac 74 alyw act 74 alyw act74 awlyww mc74act74n awlyyww 74ac74 alyw eiaj14 74act74 alyw
mc74ac74, mc74act74 http://onsemi.com 8 package dimensions pdip14 n suffix 14 pin plastic dip package case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 so14 d suffix 14 pin plastic soic package case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc74ac74, mc74act74 http://onsemi.com 9 package dimensions tssop14 dt suffix 14 pin plastic tssop package case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n eiaj14 m suffix 14 pin plastic eiaj package case 96501 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z
mc74ac74, mc74act74 http://onsemi.com 10 notes
mc74ac74, mc74act74 http://onsemi.com 11 notes
mc74ac74, mc74act74 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74ac74/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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